# Reading D:/altera_130/modelsim_ase/tcl/vsim/pref.tcl 
# do CLOCK_PCF8563_VERILOG_run_msim_rtl_verilog.do 
# if {[file exists rtl_work]} {
# 	vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Copying D:\altera_130\modelsim_ase\win32aloem/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# ** Warning: Copied D:\altera_130\modelsim_ase\win32aloem/../modelsim.ini to modelsim.ini.
#          Updated modelsim.ini.
# 
# vlog -vlog01compat -work work +incdir+D:/Redkin/Proects_PLIS/DE0_Nano/CLOCK_PCF8563_VERILOG {D:/Redkin/Proects_PLIS/DE0_Nano/CLOCK_PCF8563_VERILOG/UART_byte_tx.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module UART_byte_tx
# 
# Top level modules:
# 	UART_byte_tx
# vlog -vlog01compat -work work +incdir+D:/Redkin/Proects_PLIS/DE0_Nano/CLOCK_PCF8563_VERILOG {D:/Redkin/Proects_PLIS/DE0_Nano/CLOCK_PCF8563_VERILOG/Trigger_2st_front.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module Trigger_2st_front
# 
# Top level modules:
# 	Trigger_2st_front
# vlog -vlog01compat -work work +incdir+D:/Redkin/Proects_PLIS/DE0_Nano/CLOCK_PCF8563_VERILOG {D:/Redkin/Proects_PLIS/DE0_Nano/CLOCK_PCF8563_VERILOG/PCF8563_wr_rd.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module PCF8563_wr_rd
# 
# Top level modules:
# 	PCF8563_wr_rd
# vlog -vlog01compat -work work +incdir+D:/Redkin/Proects_PLIS/DE0_Nano/CLOCK_PCF8563_VERILOG {D:/Redkin/Proects_PLIS/DE0_Nano/CLOCK_PCF8563_VERILOG/buzzer_butt.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module buzzer_butt
# 
# Top level modules:
# 	buzzer_butt
# vlog -vlog01compat -work work +incdir+D:/Redkin/Proects_PLIS/DE0_Nano/CLOCK_PCF8563_VERILOG {D:/Redkin/Proects_PLIS/DE0_Nano/CLOCK_PCF8563_VERILOG/CLOCK_PCF8563_VERILOG.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module CLOCK_PCF8563_VERILOG
# 
# Top level modules:
# 	CLOCK_PCF8563_VERILOG
# 
# vlog -vlog01compat -work work +incdir+D:/Redkin/Proects_PLIS/DE0_Nano/CLOCK_PCF8563_VERILOG/simulation/modelsim {D:/Redkin/Proects_PLIS/DE0_Nano/CLOCK_PCF8563_VERILOG/simulation/modelsim/CLOCK_PCF8563_VERILOG.vt}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module CLOCK_PCF8563_VERILOG_vlg_tst
# 
# Top level modules:
# 	CLOCK_PCF8563_VERILOG_vlg_tst
# 
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc"  CLOCK_PCF8563_VERILOG_vlg_tst
# vsim -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs=\"+acc\" -t 1ps CLOCK_PCF8563_VERILOG_vlg_tst 
# Loading work.CLOCK_PCF8563_VERILOG_vlg_tst
# Loading work.CLOCK_PCF8563_VERILOG
# Loading work.PCF8563_wr_rd
# Loading work.buzzer_butt
# Loading work.Trigger_2st_front
# Loading work.UART_byte_tx
# 
# add wave *
# view structure
# .main_pane.structure.interior.cs.body.struct
# view signals
# .main_pane.objects.interior.cs.body.tree
# run -all
# Break in Module CLOCK_PCF8563_VERILOG_vlg_tst at D:/Redkin/Proects_PLIS/DE0_Nano/CLOCK_PCF8563_VERILOG/simulation/modelsim/CLOCK_PCF8563_VERILOG.vt line 135
# Simulation Breakpoint: Break in Module CLOCK_PCF8563_VERILOG_vlg_tst at D:/Redkin/Proects_PLIS/DE0_Nano/CLOCK_PCF8563_VERILOG/simulation/modelsim/CLOCK_PCF8563_VERILOG.vt line 135
# MACRO ./CLOCK_PCF8563_VERILOG_run_msim_rtl_verilog.do PAUSED at line 21
