# do CLOCK_PCF8563_AHDL.do 
# ** Warning: (vlib-34) Library already exists at "work".
# 
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module CLOCK_PCF8563_AHDL
# 
# Top level modules:
# 	CLOCK_PCF8563_AHDL
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module CLOCK_PCF8563_AHDL_vlg_sample_tst
# -- Compiling module CLOCK_PCF8563_AHDL_vlg_check_tst
# -- Compiling module CLOCK_PCF8563_AHDL_vlg_vec_tst
# 
# Top level modules:
# 	CLOCK_PCF8563_AHDL_vlg_vec_tst
# vsim -L cycloneive_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate -c -t 1ps -novopt work.CLOCK_PCF8563_AHDL_vlg_vec_tst 
# Loading work.CLOCK_PCF8563_AHDL_vlg_vec_tst
# Loading work.CLOCK_PCF8563_AHDL
# Loading altera_ver.dffeas
# Loading cycloneive_ver.cycloneive_lcell_comb
# Loading cycloneive_ver.cycloneive_io_ibuf
# Loading cycloneive_ver.cycloneive_clkctrl
# Loading cycloneive_ver.cycloneive_mux41
# Loading cycloneive_ver.cycloneive_ena_reg
# Loading cycloneive_ver.cycloneive_io_obuf
# Loading work.CLOCK_PCF8563_AHDL_vlg_sample_tst
# Loading work.CLOCK_PCF8563_AHDL_vlg_check_tst
# Loading altera_ver.PRIM_GDFF_LOW
# ERROR! Vector Mismatch for output port K1_OUT_PLIZ :: @time = 1000000.000 ps
#      Expected value = 0
#      Real value = 1
# ERROR! Vector Mismatch for output port K2_OUT_PLIZ :: @time = 1000000.000 ps
#      Expected value = 0
#      Real value = 1
# ERROR! Vector Mismatch for output port K3_OUT_PLIZ :: @time = 1000000.000 ps
#      Expected value = 0
#      Real value = 1
# ERROR! Vector Mismatch for output port K0_OUT_PLIZ :: @time = 5500000.000 ps
#      Expected value = 0
#      Real value = 1
#           4 mismatched vectors : Simulation failed !
# ** Note: $finish    : CLOCK_PCF8563_AHDL.vt(612)
#    Time: 100 us  Iteration: 0  Instance: /CLOCK_PCF8563_AHDL_vlg_vec_tst/tb_out
