
;	1Mhz internal
.device ATTINY2313
.cseg

.org 0

;interrupts
	rjmp	start 	;reset, watchdog
	reti		;int0
	reti		;int1
	reti		;timer1 capture
	rjmp	tm0	;timer1 compare match A
	reti		;timer1 ovf1
	reti		;timer0 ovf0
	reti		;USART RX
	reti		;USART URDE
	reti		;USART TX
	reti		;Comparator
	reti		;pin change
	reti		;timer counter 1 ompare match B
	reti		;timer counter 0 ompare match A
	reti		;timer counter 0 ompare match B
	reti		;USI start
	reti		;USI overflow
	reti		;EEPROM ready
	reti		;WatchDog

start:	
cli
	ldi 	r16, 0xDF
	out 	SPL, r16
	
	sbi 	DDRD,6
	sbi	PORTD,6
	cbi	DDRD,3
	sbi	PORTD,3
	cbi	PORTB,0
	sbi	DDRB,0
	clr	r22

	ldi r16,high(150)
	out	OCR1AH,r16
	ldi	r16,low(150)
	out	OCR1AL,r16

	clr r16
	out	TCCR1A,r16
	out	TCCR1C,r16
;clock source clk/1, CTC mode
	ldi	r16, 0b00001001 
	out	TCCR1B, r16
;set int enable for compare 1A
	ldi	r16, 0b01000000 
	out	TIMSK, r16
;enable sleep mode IDLE, falling edge INT1
	ldi	r16,0b00101000 
	out	MCUCR,r16

	in	r16,PIND
	bst	r16,3
	brts	rel
	com	r22
rel:	rcall	reload

	sei
lp:	sleep
	rjmp	lp

;====================================
tm0:	sei
	dec	r19
	breq	nb
	lsr	r21
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
send:	;+14
	cbi	DDRB,0
	bst	r21,0
	brts	one
zero:	nop
	;delay 50mcs
	ldi	r16,7	
	rcall	delay
	sbi	DDRB,0
	reti

one:		
	;delay 100 msc
	ldi	r16,17
	rcall	delay
	sbi	DDRB,0
	reti

nb:	;new byte load
	lpm	r21,Z+
	dec	r20
	cpi	r20,1	
	ldi	r19,3	
	breq	l3
	ldi	r16,5	
	add	r19,r16	
l3:	or	r20,r20
	brne	send
last:	rcall	reload
	reti
;=======================
reload:
	ldi	r20,6
	ldi	r19,1
	or	r22,r22
	brne	k2
k1:
	ldi	ZH,high(key1*2)
	ldi	ZL,low(key1*2)
	ret

k2:	ldi	ZH,high(key2*2)
	ldi	ZL,low(key2*2)
	ret
;===========================
delay:
	nop
	nop
	dec	r16
	brne	delay	
	nop
	nop
	nop
	ret
;===========================
key1:
	.db	0x4A,0x8D,0x19,0x9D,4
key2:
	.db	0x23,0x44,0x39,0x1F,1


 key1  key2         .    35           4   8  ( 3         8- )        -     . ,   00110110  0x6C.
